1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and more particularly to a nonvolatile semiconductor memory device using a variable resistive element having a first electrode, a second electrode, and a variable resistor formed between those electrodes, in which a resistance state represented by current-voltage characteristics between both electrodes is reversibly shifted to two or more different resistance states by applying a voltage between those electrodes, and the shifted resistance state can be maintained in a nonvolatile manner, and a method for producing the same.
2. Description of the Related Art
With the spread of a mobile electronic equipment, a large-capacity and inexpensive nonvolatile memory is required to be capable of holding stored data while a power is off. In order to meet the request, nonvolatile memories have been increasingly developed such as a flash memory, ferroelectric memory (FeRAM), a magnetoresistance-change memory (MRAM), a phase-change memory (PCRAM), a solid electrolyte memory (CBRAM), and resistance-change memory (RRAM) (refer to W. W Zhuang et al., “Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, IEDM Technical Digest, pp. 193 to 196, December, 2002). Among the above nonvolatile memories, the RRAM especially attracts an attention because high-speed writing can be performed, and a simple binary transition metal oxide can be used as its material, so that it can be easily produced and has high affinity for an existing CMOS process.
In a memory cell array using the RRAM, a combination of a memory cell and an array structure which can implement the highest capacity is a cross-point type memory cell array having a 1R structure. However, when the cross-point type memory cell array having the 1R structure is used, it is necessary to take measures against a leak current. Thus, as a current limit element to avoid the problem of the leak current, a memory cell structure called a 1T1R structure having a transistor, or a 1D1R structure having a diode has been proposed (refer to Japanese Patent Application Laid-Open No. 2004-363604, Japanese Patent Application Laid-Open No. 2008-198941, I. G. Baek et al., “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, IEDM Technical Digest, December, 2004, and Z. Wei et al., “Highly Reliable TaOx ReRAM and Direct Evidence of Redox Reaction Mechanism”, IEDM Technical Digest, pp. 293-296, December, 2008).
FIG. 12 is a structural cross-sectional view of a memory cell array 500 of a nonvolatile semiconductor memory device according to the above conventional technique, and FIG. 13 is an equivalent circuit diagram. In this configuration, one memory cell is composed of a selection transistor 502 and a variable resistive element 504. The selection transistor 502 is composed of a gate insulation film 510, a gate electrode 512, a drain region 514, and a source region 516, and formed on an upper surface of a semiconductor substrate 508 in which an element isolation region 506 is formed. In addition, the variable resistive element 504 is composed of a lower electrode 522, a variable resistor 524, and an upper electrode 526.
The gate electrode 512 of the transistor 502 serves as a word line (WL), and a source line (SL) 518 is electrically connected to the source region 516 of the transistor 502 through a contact plug 536 formed in a first interlayer insulation film 532. In addition, a bit line (BL) 520 is electrically connected to the upper electrode 526 of the variable resistive element 504 covered with an interlayer insulation film 534 through a contact plug 539 formed in the third interlayer insulation film 534, while the lower electrode 522 of the variable resistive element 504 is electrically connected to the drain region 514 of the transistor 502 through a contact plug 538 and a metal wiring 519 formed in a second interlayer insulation film 533, and a contact plug 537 formed in the first interlayer insulation film 532. Furthermore, the bit line 520 is also connected to a lower layer metal wiring 521 to connect to a peripheral circuit through a contact plug 535. In addition, in the memory cell array 500, the two memory cells share the one source line 518 as shown in the equivalent circuit diagram in FIG. 13.
Thus, according to the configuration in which the selection transistor 502 and the variable resistive element 504 are arranged in series, the transistor in the memory cell selected by a potential change of the word line 512 is turned on, and programming or erasing can be selectively performed only in the variable resistive element 504 in the memory cell selected by a potential change of the bit line 520.
The conventional memory cell array 500 shown in FIG. 12 is normally produced according to a flowchart shown in FIG. 14. In addition, steps in the following description correspond to steps of the flowchart shown in FIG. 14, respectively.
First, the element isolation region 506 (such as STI Shallow Trench Isolation) and the transistor 502 (such as MOS transistor) are formed on the semiconductor substrate 508 by the well-known technique, the first interlayer insulation film 532 is formed by the well-known technique, the contact plug 536 to connect to the source region 516 of the transistor 502, and the contact plug 537 to connect to the drain region 514 of the transistor 502 are formed, and the metal wiring (source line) 518 and the metal wiring 519 are formed on the contact plug 536 and the contact plug 537, respectively (step #601: metal wiring formation step).
Then, the second interlayer insulation film 533 is formed (step #602: interlayer insulation film formation step), and an opening is formed over the metal wiring 519 connected to the drain region 514 of the transistor 502 through the contact plug 537 so as to penetrate the interlayer insulation film 533 on the metal wiring 519, by the well-known technique (step #603: opening formation step).
Then, the opening over the metal wiring 519 is filled to form the contact plug 538 (step #604: plug formation step) by the well-known technique, and then the lower electrode 522, the variable resistor 524, and the upper electrode 526 of the variable resistive element 504 are sequentially deposited (step #605: lower electrode film deposition step, step #606: variable resistor film deposition step, and step #607: upper electrode film deposition step).
Then, the lower electrode 522, the variable resistor 524, and the upper electrode 526 are patterned by well-known photolithography and etching, to form the variable resistive element 504 (step #608: variable resistive element formation step).
Then, the third interlayer insulation film 534 is formed (step #609: interlayer insulation film formation step), and then the opening is formed over the upper electrode 526 of the variable resistive element 504 by the well-known technique (step #610: opening formation step).
Then, the opening over the upper electrode 526 is filled to form the contact plug 539 by the well-known technique (step #611: plug formation step) and then the metal film is deposited (step #612: metal film deposition step), and the metal film is patterned by well-known photolithography and etching, whereby the upper layer metal wiring (bit line) 520 connected to the contact plug 539 is formed (step #613: metal wiring formation step).
Thus, in producing the conventional nonvolatile semiconductor memory device, it is necessary to form the variable resistive element 504, the contact plug 538 to electrically connect the lower electrode 522 and the metal wiring 519, the contact plug 539 to electrically connect the upper electrode 526 and the metal wiring 520, and the contact plug 535 to electrically connect the lower layer metal wiring 521 in the peripheral circuit and the upper layer metal wiring 520 by repeating the process steps using photolithography, which causes the photomask number to increase, and the production steps to become complicated.